Taiwan Semiconductor Manufacturing Company (Part 2)

For the first half of this TSMC deep dive, I mainly focused on the broader semiconductor environment and how TSMC fits into the ecosystem. For the second half, I will focus on TSMC’s business from a financial and operational perspective, walking you through the unit economics, growth potential, risks and valuation approach behind my recent investment decision. 

5. Business economics

Over the past 20 years, TSMC has consistently earned an EBIT margin of at least 31% and has only fallen below 25% EBIT margins once since going public, during the 2001/02 tech bubble collapse. While volatile to some degree, TSMC's business economics are among the best across the technology industry, which I attribute to its value creation for customers and contribution to society.

Compared more broadly, TSMC scores 7.95/10 on the Jenga IP Quality ranking's profit margin sub-category (more on this in the risks section). While not as impressive as its primary customer, Apple, with an 8.45/10 score, TSMC is among the highest I have studied so far.

To truly understand its business and unit economics, I will dissect its business model and examine its revenue, costs, capital expenditures (Capex), depreciation, and ultimately, the unit economics per wafer and fab economics.

Revenue

Like every business, revenue is all about the price and volume equation. For TSMC, we can think about its revenue profile in three ways: by node/technology, platform, and by geographical region. Of these three, the most important are application and node/technology, as they provide more insights into TSMC's capabilities and customer base. In contrast, geographical regional data is less insightful, as foundry customers are global businesses that can ship the end product to customers anywhere in the world.

Revenue by node

The most important goal for a foundry is to mass-produce the most technologically advanced chips within its capacity, with high utilisation and limited defects, consistently for customers. The semiconductor industry classifies these technologies by nodes. Historically, node names, such as 800nm, 180nm, and 65nm, were tied to the physical features (gate length) of each chip. However, in the past decade, this is no longer true; 5nm had a gate length of 18nm.

That said, the names are still used according to industry standards, primarily for marketing purposes. From the chart below, you can see when each node type went into production at TSMC. As time passes, these nodes become smaller, more powerful, and more expensive.

Generally, TSMC lacks significant pricing power; however, its key method of raising prices for customers involves driving industry innovation and setting higher starting prices for its most innovative and leading-edge chips.

Over the past two decades, the prices of TSMC's latest chips have increased by 12% annually, with TSMC citing improved performance and reduced energy consumption as justification for these price increases. Another significant trend is that over the years, sales from TSMC's newest chips have grown as a share of TSMC's revenue at a faster pace (chart below), which I attribute to Apple's near-guaranteed sales of TSMC's most advanced chips for its iPhone and MacBook products.

The chart above portrays TSMC's revenue by node. Note that between 2015 and 2017, TSMC didn't publish the exact revenue figure, only percentages. Therefore, the data here are estimates to the nearest percentage. Overall, over the past 9 years, TSMC's wafer revenues have grown from TW$766 billion to TW$2,514 billion, a 14.1% CAGR, which is well ahead of the overall global foundry market growth during the period (6% per year).

First, upon examining TSMC's older chips (trailing-edge), there's no real revenue growth. Customers are more likely to obtain cheaper quotes from rival foundries for these chips, and as shown in the table below, chips above 16nm have registered barely any growth over the past nine years.

At the other end of the node spectrum, TSMC's 7nm and below chips (bottom of the chart, starting 2018) have been key to propelling its growth; in its first full production year, its 3nm chips made more revenue than all chips above 40nm node size in 2024 and half of TSMC's full revenue in 2018. Semiconductor leadership versus peers like Intel and Samsung is paramount for TSMC's revenue growth.

In the chart above, I examine TSMC's revenue as a percentage of total revenue for each node. Similarly, we observe how quickly the latest chips gain market share, driven by demand from TSMC's customers. In 2024, leading-edge chips (7nm and below) accounted for 69% of TSMC's revenue. I expect this trend to continue for years to come, underscoring the critical importance of these chips to TSMC's revenue and profitability. While the 2nm chips will be in mass production by late 2025, the 3nm chips were the most advanced node for TSMC as of the end of 2024, and it's helpful to share some insights here.

Case study - 3nm (N3) in focus

As of the end of 2024, TSMC's latest chip node, the 3nm (or N3 family), accounted for 18.3% of its 2024 revenue and is likely to account for at least 25% of its 2025 revenue, having been a success for the foundry so far. The 3nm chips were in direct competition with Samsung's 3GAE/3GAP chips and Intel 3 chips - the trio are the only companies globally that can make these chips. TSMC had announced ambitions for 3nm chips as early as 2017 and proceeded with building a new fab (Fab 18 in the Southern Taiwan Science Park) that year.

The 3nm chips enabled TSMC's clients to enhance the performance of their end-use cases, and Apple was the first to integrate the 3nm chip in the third quarter of 2023. TSMC typically builds different chip variations within each family; 3nm has N3B (B for baseline), N3E (E for enhanced), N3P (P for performance), N3X (X for extreme), and N3A (for Automotive). Each of these has its ideal applications; N3X is optimised for data centres and used in GPUs and CPUs (not yet in mass production), while the N3B was for the Apple A17 chips, used in the iPhone 15.

Overall, based on customer feedback and teardown analysis of the end products, TSMC's 3nm chips have been generally well-received in the industry. While Apple, the primary launch customer for TSMC's N3B node, experienced some battery life issues, the overall performance and efficiency gains were seen as worthwhile. Qualcomm has adopted the TSMC N3E chips for their Snapdragon 8 Gen 3 mobile chips, viewing the improvements from 5nm as an incremental leap rather than a revolutionary one. It expects to be a customer for the N3P chips.

In the table below, I compare some key specifications of TSMC N3 chips with those of their rivals, Samsung 3GAE and Intel 3. TSMC's efforts in the 3nm category significantly exceeded those of both Samsung and Intel. Samsung's 3GAE suffered from poor yields and limited commercial uptake (see customers) while the 3GAP rollout was slower than anticipated.

Non-wafer revenue

Until 2023, TSMC had described its addressable market predominantly in terms of wafer sales. However, the growth of its advanced chip packaging services to customers led to a shift in market size to the foundry 2.0 market, which is estimated to be a $250 billion opportunity. Today, this non-wafer revenue segment represents 13% of TSMC's total revenue, from 9% in 2015, growing 19.4% CAGR over the past 9 years versus 14.1% CAGR for wafer revenue.

TSMC doesn't break down its non-wafer revenue, but based on my research, advanced packaging likely accounts for two-thirds of the category's revenue and is a key part of the growth opportunity. I'll discuss the advanced packaging segment in more detail in the next part of this deep dive (Part 6: Growth Drivers).

Revenue by platform

Before 2017, TSMC had split its revenue by application (communication, computer, consumer, industrial), and transitioned its revenue segmentation by platform to better reflect how it truly segments the platforms. There are six categories: high performance computing (HPC), smartphones, the Internet of Things, automotive, digital consumer electronics, and others. Among these six, two particularly stand out in terms of revenue share: high performance computing and smartphones, which together represent 85.8% of total revenue, up from 78.7% in 2017, representing an 18.2% revenue growth CAGR, compared to 10.3% for the rest of TSMC's four other divisions.

Given that smartphone revenue is more straightforward (chips sold to smartphone customers), I'll focus more closely on the largest segment: High Performance Computing (HPC).

High Performance Computing division in focus

Until 2022, the smartphone segment had been the largest within TSMC, representing over half of revenue (52%) in 2017. However, today, the share of smartphones has declined to 35%, with HPC now leading with a 51% share of revenue. HPC covers a broad range of customers, including data centres, personal computers, cloud infrastructure and more technical segments like AI accelerators and networking. These chips are powerful from a computing and processing lens. They are exclusively within the advanced chip nodes segments (7nm and below). In the table below, I highlight some TSMC HPC customers and their respective chips, which are powered by TSMC HPC capabilities.

The HPC division is a key growth area with the potential to compound at a rate of at least 20% CAGR over the next five years.

Revenue by region

The final method for segmenting TSMC's revenue is by region. Among the three, by region is the least insightful as it defines the region by where its customer is headquartered; Apple is headquartered in the US, but 17% of its last quarter sales were in China and 26% in Europe, which makes this data point less meaningful if we are to understand the regional business drivers.

I wouldn't spend much time analysing the data point, but it's important to note the concentration in US-based customers, with an average of 65.5% of total revenue over the past ten years, and a recent high of 70% achieved in 2024, most likely driven by Nvidia's growth.

Costs

The second part of the business economics equation is costs; however, TSMC is much less open with information, detailing its cost structure and only reporting figures for cost of revenue, R&D, General and administrative, and marketing. From the company filings, we can deduce some sub-segments, such as depreciation and employee benefits. For the rest, I will rely on my estimates based on broader research into foundry and fab economics.

In the chart below, I map out TSMC's cost structure across its four cost segments. As shown, the cost of revenue represents the majority, roughly 80% of its total costs, with R&D being the second largest at 13-14% of TSMC's totals. At the other end is marketing, which accounts for just 1% of TSMC's total costs. A rule I use is that the best technical B2B businesses often have very minimal marketing spend, and TSMC's 1% allocation for marketing aligns with this criterion.

Costs of revenue

At 80% of total costs and 45-50% of revenue (see chart above), the cost of revenue is the largest segment of TSMC’s cost structure. Here, TSMC provides insights into depreciation and employee benefits (salary and pension) share of cost of revenue but for the other costs, approximately 34% of the cost of revenue segment, TSMC’s filings doesn’t explicitly state these and as part of my research, I spoke with industry experts familiar with the foundry and fab economics to gain some perspectives on what might be included here.

In the table below, I provide a clearer perspective of TSMC's economics by identifying other sub-categories within TSMC's cost of revenue structure, such as raw materials (17.3% - including wafers, chemicals, gases, and photoresists), utilities (7.5% - comprising electricity, water, and HVAC), among others. These aren't official figures from TSMC but estimates I've concluded from research into fabs and their operations. Next, I'll examine two key sub-segments: depreciation & capital expenditures (Capex), and raw materials.

Raw materials

There are five key raw materials required in the chipmaking process: wafers, chemicals, lithographic materials (also known as photoresists), gases, and polishing & contact pads. I estimate that these combined costs represent roughly NT$220 billion, or 17.3% of the cost of revenue, and will vary across fabs and locations. For example, fabs in Taiwan are likely to have lower costs than those elsewhere, due to their integrated supply chain and lower delivery costs.

TSMC also has limited control over pricing due to the supply and demand nature of most of these materials, but benefits from economies of scale when compared to other pure-play foundries, while being on equal footing relative to Samsung and Intel. A Taiwanese-based manufacturer of wafers, GlobalWafers sells more wafers to Samsung than TSMC. In my wafer unit economics calculations, I break down these costs further.

Depreciation and Capex

Depreciation is the most significant cost segment, accounting for 48.5% of TSMC's cost of revenue and 41.6% of TSMC's total costs, reflecting its asset-intensive business model. TSMC doesn't provide a specific breakdown of its depreciation, but from its filings, one can estimate that 75% is attributed to machinery and equipment, such as ASML's EUV lithography systems, Lam Research's etching equipment, and Applied Materials' Chemical Vapour Deposition (CVD) tools, among others. These are depreciated over 5-7 years and are skewed towards the newer nodes, such as 3nm and 5nm, which require larger and more expensive equipment in capital expenditures (Capex).

The rest of depreciation (25%) is likely buildings and cleanrooms, typically depreciated over 10-20 years and includes assets such as the fab buildings, cleanroom shells, HVAC & filtration systems, electrical systems, among others.

Given that depreciation accounts for over 40% of TSMC's total cost base, any misalignment between capital investment and customer demand, whether due to market cycles, overestimation of customer uptake, or delays in node transitions, poses a significant risk to the company. Since depreciation is a non-discretionary, fixed cost once assets are deployed, underutilisation of capacity directly compresses margins. This makes accurate Capex planning and demand forecasting critical levers in maintaining TSMC's industry-leading profitability.

As shown in the charts above, TSMC's depreciation experienced a sharp increase in 2021 and has more than doubled over the past four years, reflecting the current Capex cycle.

Capex cycle till date with the sheer majority of this Capex dedicated to growing its annual capacity in fabs 18 and 21, its specialty technology fabs in Japan (fab 23) and Germany (fab 24), fab 22, a Taiwan fab to be dedicated for 2nm production in H2 2025 and finally, its Arizona, USA fab (fab 21), which is expected to host 30% of TSMC's advanced chips production at full capacity upon completion.

Unit economics

My most important quantitative question when investing in any company is understanding how much it earns from one unit, which sums up the business economics analysis. In the foundry business, this is one wafer (300mm equivalent size) and here, I'll compare the economics of a single 3nm node wafer versus a 65nm node and also extend the unit economics analysis to the fab level, analysing TSMC's fab 12 (65nm chips mainly produced here), versus its Fab 18 (3nm chips produced here) to portray how its economics differ by technology.

Wafer unit economics

For the wafer unit economics, I compare the economics of a single 3nm TSMC wafer versus a 65nm wafer (300mm per wafer size).

The manufacturing processes for these two nodes differ significantly. The 3nm process involves more complex steps and requires additional materials, such as the Extreme Ultraviolet Lithography (EUV) equipment made by ASML. These differences are reflected in the estimated additional costs for machine depreciation and EUV photoresist materials. Furthermore, the 3nm node's increased number of patterning layers significantly increases etching and deposition costs, nearly tripling those at the 65nm node. Utilities, cleanroom HVAC, and general wear-and-tear costs are also higher at 3nm and have been factored into the unit economics calculations.

Based on these estimates:

• A 3nm wafer priced at $20,000 carries an estimated cost of $7,260, resulting in an estimated profit of $12,740 per wafer and a profit margin of approximately 63.7%.

• In contrast, a 65nm wafer, given its more commoditised pricing, earns around $2,500 with costs estimated at $725, leading to an estimated profit of $1,775 per wafer and a profit margin of roughly 71.0%.

Fab level unit economics

TSMC operates 14 fabs with varying economics and node focus. To provide context, I have selected two representative fabs for this analysis:

• Fab 18: Specialises in 3nm and 5nm chips and is located in the Southern Taiwan Science Park.

• Fab 12: Produces 40nm and 65nm nodes and is located in Hsinchu Science Park.

Both Fab 12 and Fab 18 are among TSMC's gigafactories, and I assume monthly wafer production exceeding 100,000 units, with Fab 12 benefiting from higher yields due to its maturity relative to Fab 18. Fab 18’s use of EUV technology, higher energy consumption, photoresists, labour, and etching materials has been reflected in the depreciation and cost estimates.

Based on these assumptions:

• I estimate Fab 18 generates annual revenue of approximately $19 billion, with estimated costs of $8 billion, resulting in annual profits near $11 billion and an estimated profit margin of 58%.

• Fab 12, despite higher wafer throughput, earns an estimated $5.2 billion annually due to lower average wafer prices. Costs are estimated at $2.1 billion, primarily due to lower depreciation, leading to profits of $3.1 billion and an estimated margin of 60.2%.

6. Growth drivers

Readers familiar with my Jenga IP investment process will be aware of our approach. For the benefit of new readers, I would like to provide a brief recap. Quality (50%), growth (25%), and value (25%) are the three key components of the investment equation. Central to TSMC's investment theme is the upside across all three objectives. Over the next five years, I expect revenue to increase at an 18% CAGR and net profits to grow at a 16% CAGR.

There are three key drivers for TSMC's growth: advancements in chip nodes, thereby increasing the price per wafer, capacity expansion led by Arizona, USA, and the opportunity in advanced packaging.

Technological node advancements

On a personal level, I was slow to appreciate the true potential and role chips played in data centres and cloud computing. It wasn't until my deep dive into Alphabet earlier this year that I began to value the productivity gains enabled by the various applications and use cases of AI. Central to the AI theme are chips, at the backbone of processing and workloads. Whether via ASICs designed by cloud computing providers and their outsourcing partners (such as Broadcom and MediaTek) or Nvidia's GPUs, all roads lead to TSMC's manufacturing capabilities.

TSMC currently dominates the leading-edge nodes, holding over 90% of the market share. While it's likely that Samsung and Intel will recover some market share (primarily due to TSMC's capacity constraints), the focus, experience, and investments of TSMC remain unmatched. As we transition to the next generation of leading-edge chips, 2nm and 1.6nm (A16 chips), this will be a key driver for TSMC's future revenue and earnings growth.

2nm node insights

Each transition to a more efficient and higher-output chip presents an opportunity for TSMC to raise prices on its leading-edge chips. While these chips, of course, require more investment and operating expenditure in manufacturing at scale (see my fab-level economics earlier), the price increase, estimated at roughly 20%, offsets these additional investments, allowing TSMC to protect its margins.

Without an engineering background, it's indeed tricky to accurately assess the 2nm performance. Therefore, I've turned to customers and experts to gain a deeper understanding of what the 2nm transition means for TSMC.

From a technological lens, the 2nm chips will be TSMC's first transition to the GAAFET from the FinFET transistor. The experts claim GAAFET reduces power consumption and has more transistors per mm², supporting its performance. Samsung had already transitioned to this technology with its 3nm chips, but issues with poor yields and power efficiency impacted its prospects.

Another technological change with the 2nm chips is the introduction of backside power delivery (BSPDN), which replaces the current front power delivery (FSPDN). This change is expected to improve power efficiency and reduce heating similarly. That said, these technological changes will certainly allow rivals to regain market share, as all players will be starting from the same point, unlike in prior leading-edge nodes, which were based on FinFET transistors, a technology that TSMC had led with a gap against its rivals.

Advanced packaging

An extension of the technology advancements for TSMC is in advanced packaging, a fast-growing segment of the semiconductor value chain. TSMC’s non-wafer sales represent 13% of its total revenue. Within this segment, I estimate around two-thirds is advanced Packaging, where TSMC helps its customers package multiple chips on a single electronics package.

Outsourced semiconductor assembly and test companies, such as the Taiwanese ASE Technology and Amkor Technology, dominated the traditional packaging market. However, lately, TSMC has made several efforts and investments to bring these packaging services in-house, alongside its fabrication services, primarily targeting customers in the HPC and AI chip market.

TSMC has developed its IP on technologies including InFO (Integrated Fan-Out) - 2D Packaging, CoWoS (Chip-on-Substrate) - 2.5D Packaging, and SoIC (System-on-Integrated-Chip) - 3D Packaging, to increase the overall performance of chips. Management expects this division to be a fast-growing solution, with customers such as Apple utilising SoIC, Nvidia utilising CoWoS for its Blackwell chip and AMD utilising InFO. Among these three, CoWoS is likely to have the largest revenue share, and I expect it to have the most meaningful impact on TSMC’s revenue. Meanwhile, SoIC’s use case for custom AI accelerators could lead to its revenue growing above 40% CAGR over the next five years.

Fab capacity expansion

At the volume growth scope, TSMC can either expand existing fabs or build new fabs. Lately, given the chip crunch induced by the pandemic and the current geopolitical climate in Taiwan, TSMC and its customers have been under pressure to localise fabs where possible.

Over the next few years, some capital expenditures will be dedicated to building new fabs in Japan, Germany, and the US. Among these three countries, TSMC's American investments in its Arizona facility are undoubtedly the most extensive and require further analysis to appreciate the long-term growth opportunity in TSMC's fab and wafer production capacity.

The Arizona opportunity

In May 2020, TSMC announced its plans to develop its first advanced US manufacturing site in Arizona, USA, scheduled over three phases with total investments estimated to be around $165 billion. Given that nearly 70% of its revenue comes from customers headquartered in the US, alongside current political ambitions to onshore manufacturing domestically, it’s not surprising for TSMC to finally prioritise investments here.

TSMC's management has guided that its Arizona fab could produce 30% of all TSMC's advanced nodes by the end of the decade, once its phase 3 stage is completed. The importance of this investment extends beyond its financial value. One of the investment cases for Intel is its onshore production capacity; however, once TSMC completes the Arizona fab at the end of the decade, its production capacity could rival Intel's current capacity, thereby nullifying the "Made in America" investment case for Intel.

Beyond Arizona, TSMC also has various fab capacity projects, and in the table below, I highlight seven fab projects, including the three Arizona phases. The Japanese Kumamoto fab (fab 23) and Germany's Dresden fab (fab 24) are both part of their respective bids to semiconductor self-sufficiency. I don't expect both to have a significant impact on TSMC's overall revenue, given their node focus. The Kumamoto fab, for example, is expected to have an annual wafer capacity of 1.2 million, which is approximately 8% of TSMC's total production capacity. However, given its focus on trailing-edge automotive chips, I expect this to be less than 3% of TSMC's overall revenue at full capacity.

These investments outside Taiwan aren't a substitute for domestic investments. Similarly, TSMC is expanding its fabs in Taiwan, with both Fab 20 (Hsinchu) and Fab 22 (Kaohsiung) expected to commence mass production in the second half of 2025. The focus is on 2nm chips, followed by A14 chips from 2028, with a combined annual capacity of 1.4 million at full production.

Overall, I expect TSMC's annual wafer capacity to reach 21 million by 2029, a 4.3% CAGR over the next five years.

7. Risks and challenges

Before diving into the risks and challenges associated with TSMC, I would like to introduce you to two new checklist tools I use at Jenga IP:

• The Jenga IP Quality checklist

• The Jenga IP risk map

TSMC - Jenga IP Quality checklist

Since I last introduced the Jenga IP Quality checklist tool during our Alphabet deep dive, I’ve extended its analysis by adding more sub-categories under each of the ten categories, scored on a total of 100 points. As before, each of the ten categories is equally weighted, with 10% allocated to each category. As a reminder, our ten quality categories are;

• New entry difficulty

• Nature of demand (purchase frequency, mission-critical for customer)

• Balance sheet strength

• Profit margin

• Market & its positioning

• Pricing power

• Value chain control

• Value created for society

• Culture

• Test of time

Below, I've attached the updated ratings of the five deep dives on Global Outperformers to date, as well as Apple, for comparative purposes.

• TSMC (Global semiconductor foundry)

• ICTSI (Philippines and EM port operator)

• ASUR (Mexican airport)

• OMA (Mexican airport)

• Alphabet (Parent of Google)

Among these six companies, Apple has the highest Jenga IP Quality score, at 85.9, while TSMC (80.2) is the highest among the five deep dives on Global Outperformers so far.

Culture

TSMC scores relatively well in several categories, but one area I haven’t discussed much in this deep dive is its culture (8.9/10). Within culture, the Jenga IP Quality Index examines five key factors;

• Length of CEO and management (9/10)

• Employee attrition (10/10)

• Compensation structure (8/10)

• Ownership alignment and insider skin in game (6/10)

• Management capital allocation track record (10/10)

Among all the companies we've reviewed to date, TSMC's culture stands out, particularly in its management quality. Among the 29 management members, 75% joined the company before 2000. Across all 29, there's an average of 24 years of TSMC experience, despite TSMC being founded only 38 years ago. This means its average management member has been at the firm for nearly two-thirds of TSMC's history. Its CEO and Chairman, C.C. Wei, joined the firm 27 years ago as the VP of the R&D division, before becoming a co-CEO in 2013.

I've discussed the history and capital allocation track record at TSMC, which scores a perfect ten. Rivals like Samsung, Intel, and GlobalFoundries could only dream of rivalling TSMC's balance sheet, which has a very healthy net cash position and minimal goodwill and asset writedowns over the past decade.

One area that culturally lets TSMC down, like many state-owned or state-enabled enterprises, is the insider skin in the game; insiders own less than 1% of outstanding shares.

Although I give TSMC a 6/10 here, this is not necessarily a negative factor given TSMC's background and government involvement. What matters more here are the results, not just incentives.

Flagged challenges from the Jenga IP Quality checklist

TSMC scored below 7/10 in two categories: value chain control (6.3/10) and nature of demand (6.8/10). It is essential to address these challenges and risks. However, before doing so, let's introduce the Jenga IP risk map.

Jenga IP Risk Map

The Jenga IP risk map follows a similar process to the quality checklist, with 10 categories and 60 sub-categories. However, rather than equal weighting among each of the ten categories, the risk map assigns a weighting per category that differs.

• Technological disruption (11%)

• Geopolitical and black swan events (10%)

• Macroeconomics (11%)

• Regulatory and legal (6%)

• Reputation (5%)

• Competition (12%)

• Balance sheet (15%)

• Revenue and supply chain (15%)

• Cost of services and production disruption (7.5%)

• Management risks (7.5%)

The weightings align with my view of each risk factor for listed companies; balance sheet and technological disruption risks are more material than management, regulatory & legal risks. Of course, this depends on the context and scenario, hence why it's more of a checklist than a final score.

Another key difference is that the higher the individual score rating, the worse the risk level (lower scores mean the particular risk is less impactful to the company). Rather than the overall score, I'm also more focused on the extremes, which are risk data that score above 8/10 (coloured in red).

Unlike the Jenga IP Quality rating, TSMC wasn't the best-performing company among the five companies analysed to date, and had more risks flagged than most; only ICTSI scored worse overall in this regard.

TSMC’s 3 flagged risks

• Technological disruption risks

• Supply chain risks

• Geopolitical risks

Among these three, there isn't much TSMC can do to control these risks, so we must accept them as part of its business model. For example, the semiconductor supply chain is highly concentrated, with many sub-oligopolistic or monopolistic market structures at various stages. TSMC is always at risk of IP infringement, major technological failures, or cyberattacks and security breaches, given its mission-critical nature for customers and society. However, the one flagged risk that deserves more attention here is the geopolitical risks at TSMC.

Geopolitics

Given its role in society, market share and interconnectivity with global supply chains, it's no surprise that TSMC has embedded geopolitical risks. However, an additional factor worsens TSMC's position: its location in Taiwan, which is in high tension with China. For many, this single issue makes TSMC uninvestable, so it's important to discuss its geopolitical situation.

The Chinese challenge is fourfold;

• Increased Capex and costs to localise the foundry operations

• Loss of access to the mainland Chinese market

• Management distractions

• Cross-strait relations and war

I. Localising Capex

We discussed TSMC's bid to localise its fabs where possible, due to geopolitical considerations, as seen in its ongoing initiatives in Germany, Japan, and the US. Unlike pure commodities like oil, iron ore, or salmon, the foundry market's barrier to entry isn't dependent on the availability of natural resources, but rather on human capital, strategy, and long-term thinking. These three factors are areas in which Taiwan far exceeds any peer, as I discussed when reviewing TSMC's history in Section 1.

As a result, the Taiwanese semiconductor industry has established the lowest-cost, most efficient, and integrated foundry supply chain. This means that any country or company seeking to compete in the semiconductor foundry market will need to out-invest Taiwan to be competitive, a process that can take decades. While not impossible, this is highly challenging, and it's more profitable for governments to encourage (or pressure) foundries like TSMC to invest more in their local markets.

For TSMC, this approach hurts gross margins, as manufacturing chips internationally cannot be as cost-effective as manufacturing in Taiwan. I account for this geopolitical issue in the gross margin.

II. Limited access to the Chinese market

At the moment, international markets (mainly the US) dictate TSMC's decision-making to some extent, and over the past decade, one of the more difficult challenges for TSMC has been accessing the Chinese market.

In 2018, TSMC opened its fab in China, Fab 16 (Nanjing, China), with a planned capacity of 240,000 300mm wafers per year, focusing on more trailing-edge chips (22/16nm). However, its progress here has been capped. TSMC isn't allowed to manufacture newer technology node chips without US export licenses, and is banned from manufacturing chips for American-prohibited companies, such as Huawei and HiSilicon.

At the time of the ban in 2020, both companies were among TSMC's major customers. In the following year, revenue from Chinese-headquartered companies fell by 30%. China is, of course, a significant market for semiconductors, AI, and consumer electronics. Global geopolitical tensions have financially impacted TSMC, allowing its Chinese rivals, such as SMIC, to gain some market share in the domestic market.

III. Management distractions

While geopolitics affects every major multinational company, the impact on TSMC is far more severe when compared to its peers. The time and effort that TSMC's management could have allocated towards supporting its R&D and technology roadmap is constantly diverted by geopolitics, which could be a long-term distraction for the company. It's challenging to assign a financial value to this challenge, but so far, TSMC's management has handled it effectively, as evidenced by its continued technological leadership, customer feedback, and existing growth ambitions.

IV. Cross-strait relations and potential war

The single most significant risk with TSMC is the cross-strait tensions between Taiwan and mainland China. It's why many superinvestors, like Warren Buffett, have hesitated to invest in TSMC, not because of any flaw in the business, but due to the geopolitical realities. The final chapters of Chip War by Chris Miller offer a sobering and insightful perspective on this issue. And while it's tempting to run models projecting alternate futures, e.g. Taiwan fabs offline but Arizona covering 30% of production, the impact of war goes far deeper than numbers. There's a psychological and emotional impact on Taiwanese employees, loss of talent, diminished focus and an overall dampened spirit.

To truly invest in TSMC, one must believe that, although there's some potential for war, it doesn't occur, at least during one's holding period. I share this view for one key reason: the cost for both China, the US & its allies. The disruption of Taiwan would be catastrophic not only to Taiwan but also to China and the global economy as a whole. The economic cost to China could outweigh the benefits of attempting to forcibly take Taiwan and TSMC. China's growth model still relies heavily on exports and access to Western markets; a military invasion would not only invite sweeping sanctions but also sever China's economic ties with the US, Europe, and Japan.

While hope isn't an investment strategy, a degree of geopolitical faith is required to unlock TSMC's true potential. It's not naive optimism, but rather the belief that the cost of war far outweighs the benefits for all parties involved.

Value chain control

Foundries respond to market demand from customers (such as Apple, Nvidia, and AMD) and have limited say or power in determining the medium-term market growth rates, which poses a significant challenge for TSMC. During technology boom periods, such as the current one, TSMC is under pressure to increase its capital expenditure to meet customer demands, as failing to do so could prompt customers to diversify their foundry partners to compensate for the shortfall. This is particularly critical during technological node transitions (e.g., 3nm to 2nm, as with H2 2025), as any shortfall could cause long-term problems should alternative providers like Intel and Samsung, or worse, new players like Japan’s Rapidus (backed by eight companies), actually prove to be viable foundry solutions.

TSMC has won several customers over the years and could also lose customers due to the same reason. To overcome this challenge, TSMC has responded by expanding its Capex to $38-42 billion in 2025, a 37% increase, and building new fabs to cater to its customers, as discussed in the growth driver segment. Of course, this must be carried out with moderation, as overbuilding will lead to detrimental impacts on its balance sheet and margins, as we saw during the tech bubble burst (see the tech bubble case study in Section 1 - History of TSMC).

Nature of demand - AI bubble?

At the end of my analysis is a simple yet arguably the most critical question in the TSMC investment case: Are we in an AI bubble?

I'm not sure. There are signs, but I will leave this answer for you to decide. However, suppose we consider the long-term demand replacement cycle for chips and foundry services. In that case, TSMC is exposed to this challenge and risk.

Data centres and the broader High Performance Computing (HPC) chips typically last 3-5 years during boom periods (Nvidia argue even 2 years). Cloud providers are under increased pressure to invest in the latest technologies during these periods; Meta, Amazon, Microsoft, and Alphabet have seen their capital expenditures as a percentage of revenue rise, primarily driven by the adoption of AI chips. During these periods, the replacement cycle for AI chips shortens. If we are genuinely in an AI bubble and demand collapses, these replacement cycles could extend to even 6 or 7 years across cloud providers. Longer replacement times increase the return on investment in these chips, but at TSMC's cost as they reduce the frequency of demand for TSMC's services, impacting its financial profile.

There isn't much TSMC can do beyond ensuring it delivers the best-performing and most efficient chips for customers at reasonable prices, which makes it slightly more challenging for both investors and TSMC itself to accurately forecast real demand through the cycle.

An important question is how we account for these three significant risks, as well as other risks and challenges (competition from Intel and Samsung, market entry of Rapidus). I've approached this in two ways: adjusting our future earnings growth, particularly for 2027 and 2028, and the exit multiple I'd be willing to pay for TSMC shares. In the final section, I will walk you through my valuation process for TSMC.

8. Valuation

Valuing TSMC, like any listed company, involves two processes: an intrinsic and relative approach. I integrate both and I explain how I've arrived at a potential IRR of 17.5% over the next 4.5 years.

You can view the detailed valuation model here.

Questions under consideration

As a starting point, we have to contextualise TSMC's fundamentals to its peers and the three key questions under consideration are:

• Does TSMC deserve a premium/discount to the market?

• Does TSMC deserve a premium/discount to other Taiwanese companies?

• Does TSMC deserve a premium/discount to other semiconductor companies?

In the table above, I compare TSMC's performance relative to the global average, the Taiwanese stock market, and the semiconductor index (large caps) across five quality metrics, three growth metrics, and four valuation metrics. According to the table, TSMC outperforms each benchmark in terms of both quality and growth, but is valued at multiples higher than the Taiwanese stock market index.

More insightful is the significant gap between TSMC's quality and the semiconductor industry average. TSMC achieves profitability (NI margin, EBIT margin, ROE and ROC) more than twice that of its semiconductor peers. Despite also growing faster than the average globally listed company (sell-side forward 2-year EPS estimate of 21.8% versus the market's 9%), TSMC trades at a slight discount on a forward EV/EBIT basis. Of course, the volatility in the foundry and broader semiconductor market might account for some of this, but overall, TSMC deserves a premium relative to all three benchmarks.

After considering the overall business quality of TSMC, both quantitatively and qualitatively, and given my earnings growth outlook of 15.8% CAGR over the next five years, I concluded that a 23x exit multiple is appropriate.

Revenue assumptions

• I expect TSMC's revenue to grow by 16% CAGR over the next 5 years.

• The HPC division is expected to be the fastest-growing during the period, compounding at a 20.4% CAGR, versus 10.6% for the rest of TSMC's divisions. HPC's share of revenue climbs to 61.5% by 2029

• Geographically, I expect North America to gain the most revenue share, driven by higher growth expectations from its US-headquartered customers and the Arizona fab effect.

• From a technology node perspective, its current 3nm node is expected to peak at a 27% share of wafer revenue in 2026.

• The TSMC 2nm node modelled to commence sales in 2025, with an initial 2.3% share of revenue, before reaching a peak of 28.5% in 2028

• Its 1.4nm (A14) chips commence sales in 2028 and reach 19.7% share of revenue in 2029.

• Non-wafer revenue is expected to increase from 13% in 2024 to 16% in 2029, driven by opportunities in advanced packaging for its leading-edge chips.

Costs

• Investments in fabs (Arizona, Taiwan, Japan and Germany) and additional equipment will impact its cost of revenue (depreciation included). I expect its costs of revenue to grow by 15.8% CAGR between 2024 and 2029, with gross margins decreasing from 57.6% in 2025 to 56.57% in 2029 (-1.09%).

• R&D as a percentage of revenue is maintained at 7-8%, while marketing costs are maintained at 0.4-0.5% of revenue.

• For the investment period, I haven't factored in any potential gains or losses from the sale of assets or investments, asset writedowns, or other unusual items.

• The income tax rate as a percentage of EBIT is expected to be between 17% and 18%.

Profits

• The net effects from revenue and costs bring TSMC's net profits to NT$1.5 trillion in 2029 and are expected to grow by 15.3% CAGR between 2024 and 2029.

• Net profit margins are expected to decrease from 40.5% in 2024 to 39.3% in 2029.

• I expect TSMC's capital expenditure intensity to remain elevated throughout the investment period, with the free cash flow growing from NT$870 billion in 2024 to NT$1.8 trillion (15.8% CAGR) in 2029.

Valuations

• I expect an exit multiple of 23x, justified by TSMC's above-average (relative to peers and the broader market) earnings quality, profitability & return on investment capital and earnings growth potential (15.3% 5-year EPS growth potential).

• With a dividend payment of 30% of net profits, I expect a 10.5% yield from TSMC's dividend payments during the 5 years.

• Overall, this brings TSMC to a 2029 market capitalisation of NT$57.9 trillion, or NT$2,120 per share, with a total return of 106.9% over the next 4.5 years, or an IRR of 17.53%.

Conclusion

TSMC is arguably the most critical company in civilisation today, serving as a bedrock for innovation and technological progress. In my view, its investment case is a rare opportunity that offers very high-quality business characteristics (Jenga IP Quality score of 80), earnings growth potential (16% earnings CAGR over the next five years), and is undervalued (16x 2026 earnings) compared to its peers and other major technology companies globally.

I expect TSMC to remain a staple in the Jenga IP portfolio for the next few years, of course, dependent on its valuations, opportunities we see elsewhere and how I assess the cross-strait tensions over time. TSMC currently accounts for 5.5% of our position and will adjust its weighting over time, depending on the price relative to our valuation (see the annual end-year target price in the valuations model).

I’ve also built a watchlist of key performance indicators (KPIs) beyond its monthly revenue, which is published, to track TSMC’s progress. These enable me to closely follow and monitor TSMC’s innovation and progress in comparison to its two main rivals, Samsung and Intel.

For me, my research in semiconductors will extend beyond TSMC; it’s too important to ignore. Next, I will be reviewing both ASML and Applied Materials (both have advanced to our watchlist), and I plan on spending more time on earnings calls of semiconductor companies and industry trade shows or conferences learning more about the broader sector. There’s a technical barrier to entry in the semiconductor industry, and the only way to overcome it is by being as informed as possible.

Lastly, a few readers asked for book and materials recommendations on semiconductors after I published the first part of the TSMC deep dive, and the following materials were helpful for me in understanding TSMC and the broader semiconductor industry:

• Chip War by Chris Miller

• Fabless: The Transformation of the Semiconductor Industry by Daniel Nenni

• SemiWiki by Daniel Nenni

• The Man Behind the Microchip: Robert Noyce and the Invention of Silicon Valley by Leslie Berlin

• The Microchip Revolution: A brief history by Luc Olivier Bauer

• SemiAnalysis Research by Dylan Patel (worth subscribing)

• TSMC Founder Morris Chang on the evolution of the semiconductor industry Interview

• Morris Chang in conversation with Jensen Huang Interview

• Acquired: The Complete History & Strategy of TSMC Podcast

• Acquired: TSMC Founder Morris Chang Episode 1

• Our History of David Lam, founder of Lam Research Interview

• Navigating the Costly Economics of Chip Making by Boston Consulting Group Research

• GlobalFoundries Prospectus Form F-1

• ASML 2024 Annual Report